1. Field of the Invention
This invention relates to a method of providing a bipolar transistor within a CMOS process flow and, more specifically, to a method of providing a vertical NPN transistor within a CMOS process flow.
2. Brief Description of the Prior Art
Bipolar transistors are better suited to high current applications than are MOS transistors. Furthermore, bipolar transistors are often better suited to analog applications than are MOS transistors since they provide better current and voltage matching, a wider range of linear gain and typically better frequency response and lower noise.
Parasitic bipolar devices are occasionally used in conjunction with CMOS technology to perform special circuit functions. These bipolar devices, which are typically lateral devices built across well boundaries, exhibit very poor device characteristics and are not fully isolated. Such lateral bipolar transistors are defined by lithography and therefore are relatively wide in geometry, relatively slow in operation and have high resistance. These. lateral transistor have a high ratio of peripheral and contact area, to actual device area.
It is therefore apparent that integration of vertical NPN and, PNP bipolar transistors with CMOS transistors is desirable and such integration exists in a variety of BiCMOS technologies. However, in these process flows, many additional masking and deposition steps are required to achieve a compromise optimization of the bipolar and CMOS transistors with typical added process steps of from about 50 to 100% in number through the silicide step compared to the basic standard CMOS process flow. Whereas the performance of these bipolar devices is superior to the bipolar devices fabricated by the process flow of the present invention, these process flows cannot approach the simplicity of the disclosed vertical NPN transistor. No prior art having a "free" vertical NPN transistor within a CMOS process flow is known.
It is therefore apparent that integration of a higher performance bipolar transistor and particularly a higher performance NPN transistor in a CMOS process flow is highly desirable wherein a great deal of added complexity is not added to the process flow to achieve this goal.